Synopsis

Modern electronic testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90 nanometers or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and can reach 40% of today's overall product cost. In order to tackle the problems associated with testing semiconductor devices, it is essential to attack them at the earliest possible design stages. This has led to the methodologies and technologies of design for testability (DFT).

This book is a comprehensive guide to new DFT techniques that will show the readers how to design a testability and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

Most up-to-date coverage of design for testability, logic built-in self-test (BIST), test compression, logic diagnosis, memory BIST, memory built-in self-repair (BISR), IEEE standard (1149.1, 1149.6 and 1500), and analog and mixed-signal testing.

• First comprehensive treatment in at-speed testing for logic BIST applications.
• Recent advances in test compression reducing scan test cost by at least 10X.
• The only book with coverage of memory fault simulation, DRAM BIST and memory BISR.
• Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
• Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
• Companion website (http://www.books.elsevier.com/companions) allowing the reader to download the DFT and testing software developed by Syn Test Technologies (Sunnyvale, CA), free of charge. Exercise solutions and lecture slides are available for instructors.

Table Of Contents

• Preface
• In the Classroom
• Acknowledgments
• Contributors
• About the Editors
• 1. Introduction
• 2. Design for Testability
• 3. Logic and Fault Simulation
• 4. Test Generation
• 5. Logic Built-In Self-Test
• 6. Test Compression
• 7. Logic Diagnosis
• 8. Memory Testing and Built-In Self-Test
• 9. Memory Diagnosis and Built-In Self-Repair
• 10. Boundary Scan and Core-Based Testing
• 11. Analog and Mixed-Signal Testing
• 12. Test Technology in the Nanometer Age
• Index

• Hardcover
• Publisher: Elsevier; Edition: 1st (2011)
• Language :  English
• ISBN: 9789380501550